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INTEGRATED CIRCUITS
DATA SHEET
For a complete data sheet, please also download:
* The IC06 74HC/HCT/HCU/HCMOS Logic Family Specifications * The IC06 74HC/HCT/HCU/HCMOS Logic Package Information * The IC06 74HC/HCT/HCU/HCMOS Logic Package Outlines
74HC/HCT158 Quad 2-input multiplexer; inverting
Product specification File under Integrated Circuits, IC06 December 1990
Philips Semiconductors
Product specification
Quad 2-input multiplexer; inverting
FEATURES * Inverting data path * Output capability: standard * ICC category: MSI GENERAL DESCRIPTION The 74HC/HCT158 are high-speed Si-gate CMOS devices and are pin compatible with low power Schottky TTL (LSTTL). They are specified in compliance with JEDEC standard no. 7A. The 74HC/HCT158 are quad 2-input multiplexers which select 4 bits of data from two sources and are controlled by a common data select input (S). The four outputs present the selected data in the inverted form. The enable input (E) is active LOW. When E is HIGH, all the outputs (1Y to 4Y) are forced HIGH regardless of all other input conditions. QUICK REFERENCE DATA GND = 0 V; Tamb = 25 C; tr = tf = 6 ns
74HC/HCT158
Moving the data from two groups of registers to four common output buses is a common use of the "158". The state of S determines the particular register from which the data comes. It can also be used as a function generator. The device is useful for implementing highly irregular logic by generating any four of the 16 different functions of two variables with one variable common. The "158" is the logic implementation of a 4-pole, 2-position switch, where the position of the switch is determined by the logic levels applied to S. The logic equations for the output are: 1Y = E.(1l1.S + 1l0.S) 2Y = E.(2l1.S + 2l0.S) 3Y = E.(3l1.S + 3l0.S) 4Y = E.(4l1.S + 4l0.S) The "158" is identical to the "157" but has inverting outputs.
TYPICAL SYMBOL tPHL/ tPLH PARAMETER propagation delay nI0, nI1 to nY E to nY S to nY CI CPD Notes 1. CPD is used to determine the dynamic power dissipation (PD in W): PD = CPD x VCC2 x fi + (CL x VCC2 x fo) where: fi = input frequency in MHz fo = output frequency in MHz (CL x VCC2 x fo) = sum of outputs CL = output load capacitance in pF VCC = supply voltage in V 2. For HC the condition is VI = GND to VCC For HCT the condition is VI = GND to VCC - 1.5 V ORDERING INFORMATION See "74HC/HCT/HCU/HCMOS Logic Package Information". input capacitance power dissipation capacitance per multiplexer notes 1 and 2 CONDITIONS HC CL = 15 pF; VCC = 5 V 12 14 14 3.5 40 13 16 16 3.5 40 ns ns ns pF pF HCT UNIT
December 1990
2
Philips Semiconductors
Product specification
Quad 2-input multiplexer; inverting
PIN DESCRIPTION PIN NO. 1 2, 5, 11, 14 3, 6, 10, 13 4, 7, 9, 12 8 15 16 SYMBOL S 1I0 to 4I0 1I1 to 4I1 1Y to 4Y GND E VCC NAME AND FUNCTION common data select input data inputs from source 0 data inputs from source 1 multiplexer outputs ground (0 V) enable input (active LOW) positive supply voltage
74HC/HCT158
Fig.1 Pin configuration.
Fig.2 Logic symbol.
Fig.3 IEC logic symbol.
December 1990
3
Philips Semiconductors
Product specification
Quad 2-input multiplexer; inverting
74HC/HCT158
FUNCTION TABLE INPUTS E H L L L L Notes 1. H = HIGH voltage level L = LOW voltage level X = don't care S X L L H H nI0 X L H X X nI1 X X X L H OUTPUT nY H H L H L
Fig.4 Functional diagram.
Fig.5 Logic diagram.
December 1990
4
Philips Semiconductors
Product specification
Quad 2-input multiplexer; inverting
DC CHARACTERISTICS FOR 74HC For the DC characteristics see "74HC/HCT/HCU/HCMOS Logic Family Specifications". Output capability: standard ICC category: MSI AC CHARACTERISTICS FOR 74HC GND = 0 V; tr = tf = 6 ns; CL = 50 pF Tamb (C) 74HC SYMBOL PARAMETER min. tPHL/ tPLH propagation delay nI0, nI1 to nY propagation delay E to nY propagation delay S to nY output transition time +25 typ. 41 15 12 47 17 14 47 17 14 19 7 6 max. 125 25 21 145 29 25 145 29 25 75 15 13 -40 to +85 min. max. 155 31 26 180 36 31 180 36 31 95 19 16 -40 to +125 min. max. 190 38 32 220 44 38 220 44 38 110 22 19 ns UNIT
74HC/HCT158
TEST CONDITIONS VCC WAVEFORMS (V) 2.0 4.5 6.0 2.0 4.5 6.0 2.0 4.5 6.0 2.0 4.5 6.0 Fig.7
tPHL/ tPLH
ns
Fig.6
tPHL/ tPLH
ns
Fig.7
tTHL/ tTLH
ns
Figs 6 and 7
December 1990
5
Philips Semiconductors
Product specification
Quad 2-input multiplexer; inverting
DC CHARACTERISTICS FOR 74HCT For the DC characteristics see "74HC/HCT/HCU/HCMOS Logic Family Specifications". Output capability: standard ICC category: MSI Note to HCT types
74HC/HCT158
The value of additional quiescent supply current (ICC) for a unit load of 1 is given in the family specifications. To determine ICC per input, multiply this value by the unit load coefficient shown in the table below.
INPUT nI0 nI1 S E
UNIT LOAD COEFFICIENT 0.40 0.40 2.80 0.60
AC CHARACTERISTICS FOR 74HCT GND = 0 V; tr = tf = 6 ns; CL = 50 pF Tamb (C) 74HCT SYMBOL PARAMETER min. tPHL/ tPLH tPHL/ tPLH tPHL/ tPLH tTHL/ tTLH propagation delay nI0, nI1 to nY propagation delay E to nY propagation delay S to nY output transition time +25 typ. 16 19 19 7 max. 30 35 35 15 -40 to +85 min. max. 38 44 44 19 -40 to +125 min. max. 45 53 53 22 ns ns ns ns 4.5 4.5 4.5 4.5 Fig.7 Fig.6 Fig.7 Figs 6 and 7 UNIT VCC WAVEFORMS (V) TEST CONDITIONS
December 1990
6
Philips Semiconductors
Product specification
Quad 2-input multiplexer; inverting
AC WAVEFORMS
74HC/HCT158
(1) HC : VM = 50%; VI = GND to VCC. HCT: VM = 1.3 V; VI = GND to 3 V.
Fig.6
Waveforms showing the enable input (E) to output (nY) propagation delays and the output transition times.
(1) HC : VM = 50%; VI = GND to VCC. HCT: VM = 1.3 V; VI = GND to 3 V.
Fig.7
Waveforms showing the data input (nI0, nI1) to output (nY) propagation delays and the output transition times.
PACKAGE OUTLINES See "74HC/HCT/HCU/HCMOS Logic Package Outlines".
December 1990
7

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